Phase locked loop (PLL) circuits are well known in the art. A block diagram illustrating an example prior art phase locked look (PLL) circuit is shown in FIG. 1. The typical PLL circuit, generally referenced 170, comprises phase detector 172, loop filter or low pass filter (LPF) 174 and voltage controlled oscillator (VCO) 176.
In operation, a frequency reference clock signal, often derived from a crystal oscillator, is input to the phase detector along with the VCO output signal (often divided down). The phase detector, typically implemented as a charge pump or mixer, generates a phase error (PHE) proportional to the phase difference between the reference clock input signal and the VCO output clock signal. The resultant PHE signal is then low pass filtered to yield a slow varying frequency command signal that controls the frequency of the VCO. The frequency command signal is input to a VCO or digitally controlled oscillator (DCO) such that the VCO output frequency/phase is locked to the reference clock with a certain fixed relationship. This oscillator generates an RF signal whose frequency depends on the frequency command signal.
In wireless communication systems, e.g., GSM, UMTS, Bluetooth, WiFi, etc., the RF synthesizer is a fundamental block that is used to provide a high quality, high frequency RF carrier for the transmitter and a local oscillator clock for the receiver, whose output frequency can range from several hundreds of MHz to several GHz. Different applications with different standards require different RF frequencies with different RF performance requirements. The RF clock generating the RF carrier plays a critical role in the entire wireless communication system. The quality of the RF clock directly affects the communication performance and often is the determining factor whether the system meets standards specifications.
Typically, the RF synthesizer is implemented using a phase locked loop (PLL) typically using a pure hardwired (i.e. largely fixed hardware with limited reconfigurability) design approach. All digital phase locked loops (ADPLLs) for RF synthesizer construction targeting wireless communications are known in the art. Conventional ADPLL circuits, however, are implemented as fixed hardware based (or hardwired) with limited reconfigurability. It is thus difficult for one design to readily support multi-standard wireless applications, e.g., GSM, GPRS, EDGE, WCDMA, etc. as well as wireless data networks, such as Bluetooth, WiFi and WiMAX.
Once a hardwired circuit design is committed to a physical implementation, there is little that can be changed regarding the transfer function or operation of the ADPLL. Any modification requiring logic and interconnect change results in numerous time consuming steps within the ASIC creation process (i.e. timing closure, physical design, etc.) typically requiring significant engineering resources and months of delay to launch a product. In addition, once the silicon is manufactured, any change to the ADPLL architecture makes an even costlier impact, making such changes virtually impractical.
In general, a main difference between a hardwired implementation and a microprocessor based implementation is that the microprocessor implementation uses shared hardware running at higher speed, while the hardwired implementation uses dedicated hardware running at lower speed. A block diagram illustrating an example prior art generalized processing block using a dedicated hardware implementation is shown in FIG. 2. The hardwired implementation, generally referenced 10, comprises a plurality of dedicated hardware blocks 12 for each function 14. The circuit provides memory (Mem1, Mem2, Mem3, Mem4) and dedicated hardware for each function (F1, F2, F3, F4), wherein each block runs at the data path speed fs.
A block diagram illustrating an example prior art generalized processing block using a processor based implementation is shown in FIG. 3. The circuit, generally referenced 16, comprises instruction memory 18, instruction fetch 20, instruction decode 22, ALU 24, data bus 29, register file 26 and data memory 28. The processor based solution has one shared hardware block ALU that can be configured to execute any of the four functions (F1, F2, F3, F4). The ALU is programmed by the instructions stored in instruction memory 18 and the ALU is adapted to run four times faster (4fs) to complete the data processing within the data path speed of fs.
With CMOS process technology currently advancing from 65 nm to 45 nm to 32 nm, transistors are becoming faster and faster. The interconnections, however, are becoming more and more dominant in SOC design regarding the delay and area contribution. The interconnections in a hardwired design having a large area will significantly slow the circuit speed while adding a significant silicon area overhead. Since processor based solutions run at higher speed with shared hardware, resulting in smaller area, advancements in semiconductor technology will make processor based solutions more and more attractive. This further favors use of multiple but smaller processors with a dedicated instruction set rather than one processor with a more general instruction set.
Furthermore, in conventional ADPLL circuits, the digital part of local oscillator (DLO) (i.e. a portion of the ADPLL) is implemented using dedicated random logic gates. Thus, all computations are launched on the rising edge of the ADPLL system reference clock and latched on the next rising edge. Since a majority of the circuit switching activity is centered on the rising edge of the system reference clock, most of the digital current is being switched at that point as well, creating large current transients. These digital current surges find their way into on-chip DCO, LNA, mixer and PA circuit nodes via various coupling mechanisms, e.g., capacitive, etc. These disturbances at the system clock rate have strong harmonics that are upconverted into sensitive areas of the RF spectrum, resulting in unacceptable RF spurious tones.
It is thus desirable to have a processor based PLL architecture that is software based and programmable. The programmable PLL should provide a reconfiguration capability which eases silicon debugging and development tasks and provides multi-standard operation capability. Further, the software based PLL architecture should create significantly lower current transients thus reducing the generation of spurs in the output spectrum. At the same time, the unavoidable spurious energy that is generated by the logic activity and coupled into RF circuits should be pushed higher in frequency where they lie outside of or can be easily filtered out of critical frequency bands.